San Francisco, Sep 7 As chip packaging gets more advanced, Intel has said it aspires to put a trillion transistors in a package by 2030 with his next-generation chip packaging technology.
Intel has led the industry in advanced packaging for a couple of decades.
Its innovations include EMIB (embedded multi-die interconnect bridge) and Foveros, technologies that allow multiple chips on a package to be connected side by side (EMIB) or stacked on top of one another in a 3D fashion (Foveros).
“As Moore's Law has been progressing, traditional scaling has been slowing down,” said Ann Kelleher, executive vice president and general manager of Intel’s Technology Development.
“But as we start doing advanced packaging and heterogeneous integration, it means we can pack a lot more components into a given package and a given product,” Kelleher said in a statement.
Intel’s packaging technology is also a competitive advantage for Intel Foundry Services (IFS).
“From our Foundry customers, the feedback is, one, that we're a trusted technology company that has a proven track record in both of standard packaging and advanced packaging,” said Mark Gardner, senior director of Foundry Advanced Packaging with IFS.
“And because we have such scale, we have a capacity and a geographic footprint that makes us much more diverse than some of the suppliers they work with today,” Gardner added.
Once given little attention in chipmaking, packages are changing how chips are designed and created – and, ultimately, what chips can do, according to the chip major.
“The world’s most intricate and high-tech package is one you likely never see,” said the company.
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